A Study Regarding the Implementation with VHDL of a Multiple Clock Gating Scheme for Low Power RTL Design
نویسندگان
چکیده
In this paper we propose an algorithm, implemented with VHDL language in RTL design, capable of reorganizing the f1ip-flops from within a circuit in order to reduce the power consumption through optimal c10ck distribution. Practically in the end, starting from this algoritbm, we will model the clock bebavior in a sequential circuit. Experimental results show tbat these designs have ideal logic functionality witb lower power dissipation compared to traditional designs
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تاریخ انتشار 2012